1 ? an 9999.0 unislic14 and the idt821054/64 programmable quad codec reference design using the unislic14 and the idt821054/64 programmable quad codec the purpose of this application note is to provide a reference design for the unislic14 and idt821054/64 programmable quad codec. the network requirements of many countries require the analog subscriber line circuit (slic) to terminate the subscriber line with an impedance for voiceband frequencies which is complex, rather than resistive (e.g. 600 ?) . the unislic14 accomplishes this impedance matching with a single network connected to the z t pin. the idt821054/64 quad pcm codec uses an intergrated programmable dsp to realize ac impedance matching, transhybrid balance, frequency response correction and gain setting functions. discussed in this application note are the following: ? 2-wire impedance matching. ? receive gain (4-wire to 2-wire) and transmit gain (2- wire to 4-wire) calculations. ? reference design for both 600 ? and 200 ? +680?||0.1 f (china complex impedance). impedance matching impedance matching of the unislic14 to the subscriber load is important for optimization of 2 wire return loss, which in turn cuts down on echoes in the end to end voice communication path. it is also important for maintaining voice signal levels on long loops. impedance matching of the unislic14 is accomplished by making the slic?s impedance (z o , figure 1) equal to the desired terminating impedance z l , minus the value of the protection resistors (r p ). the formula to calculate the proper z t for matching the 2-wire impedance is shown in equation 1. with the unislic14 programmed to match a zl of 600 ? , the idt821054/64 uses an intergrated programmable dsp to realize any ac impedance. the value of z t with 30 ? protection resistors is108k ? . the closest standard value is 107k ?. slic in the active mode figure 2 shows a simplified ac transmission model of the unislic14 and the connection of the idt821054/64 to the slic. circuit analysis of the unislic14 yields the following design equations: substitute equation 3 into equation 4 z t 200 z tr 2r p ? () ? = (eq. 1) v a = i m 2r s 1 80k --------- - 200 z tr 2r p ? () 5 (eq. 2) v a i m 2 ------- z tr 2r p ? () = (eq. 3) v rx 500k ------------ - - v a 500k ------------ - = i x node equation (eq. 4) at unislic14 v rx input i x v rx 500k ------------ - - i m z tr 2r p ? () 1000k ----------------------------------------- = (eq. 5) i x 500k - v tr + i x 500k = 0 loop equation (eq. 6) at unislic14 feed amplifier and load figure 1. impedance matching tip ring v rx v tx z l v 2w vs z o z tr v tr + - + - z t z t ptg floating z t r p 30 ? r p 30 ? resistive z l = z tr = 600 ? z t = 200(600 - 2*30) z t 108k ? intersil unislic14 std. value 107k ? c tx 0.47 f c rx 0.47 f application note may 2002 author: don lafontaine caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 substitute equation 5 into equation 6 substitute equation 7 into equation 8 substituting -v 2w /z l into equation 9 for i m and rearranging to solve for v 2w results in equation 10. where: v rx = the input voltage at the v rx pin. v a = an internal node voltage that is a function of the loop current detector and the impedance matching networks. i x = internal current in the slic that is the difference between the input receive current and the feedback current. i m = the ac metallic current. r p = a protection resistor (typical 30 ? ). z t = an external resistor/network for matching the line impedance. v tr = the tip to ring voltage at the output pins of the slic. v 2w = the tip to ring voltage including the voltage across the protection resistors. z l = the line impedance. z o = the source impedance of the slic . z tr = the input impedance of the slic including protection resistors. receive gain (v rx to v 2w ) 4-wire to 2-wire gain across the unislic14 is equal to the v 2w divided by the input voltage v rx , reference figure 2.the receive gain is calculated using equation 10. equation 11 expresses the receive gain (v rx to v 2w ) in terms of network impedances. from equation 1, the value of z t was set to match the line impedance (z l ) to the unislic14 plus the protection resistors (z o + 2r p ). this results in a 4-wire to 2-wire gain of -1, as shown in equation 11. v tr 2v rx i m z tr 2r p ? () ? = (eq. 7) v 2w -i m 2r p + v tr = 0 loop equation (eq. 8) at tip/ring interface v 2w i m z tr 2v rx ? = (eq. 9) v 2w 1 z tr z l ---------- - + ?? ?? ?? 2 ? v rx = (eq. 10) g 4-2 = v 2w v rx ----------- - = -2 z l z l z o + + 2 rp --------------------------------------- - -2 z l z l z l + ------------------- - 1 ? == (eq. 11) v rx tip ring z tr e g v tr i m v tx r p r p + - + - - + v rx + - i m z l figure 2. unislic14 simplified ac transmission circuit and idt821054/64 + - 500k r s + - 500k r s z t 500k 500k 500k 500k ptg + - i x v a = i m (z tr -2r p ) i x i x + - i x + - + - + - i m + - 20 ? 20 ? 1/80k = 200 (z tr - 2r p ) a = 1 i x 2 r int 20 ? r int 20 ? v 2w + - 5 intersil unislic14 v tx v in dr1/dd dx1/du idt821054/64 d/a and filter vout1 filter and a/d pcm/gci interface dsp core channel 1 channel 2 channel 3 channel 4 vin1 floating (1 of 4) an9999
3 receive gain across the system the receive gain across the system is defined as the gain from the pcm highway to the phone (v 2w ). with the receive gain through the unislic14 set to 1, the receive gain across the system is entirely controlled by programming the idt821054/64. the idt821054/64 can program the receive gain across the system in two ways (reference figure 3). ? the first is by programming the signal gain in its analog form. the analog receive gain, also known as digital to analog (d/a) gain, can be programmed in the idt821054/64 to be either 0db or -6db. ? the second is by programming the signal gain (via. coefficients) when its in digital form. the digital form of the receive path can be programmed from +3 to -12db with minimum 0.1db steps. this results in a possible receive gain (d/a) programming range from +3db to -18db. note: analog gain brings less noise than digital gain. when allocating the codec gain, the majority of the required gain should be preformed in the analog stage. reference section titled ?information required for idt to calculate idt821054/64 codec dsp coefficients? for information on obtaining coefficients for your design. transmit gain across unislic14 (e g to v tx ) the 2-wire to 4-wire gain is equal to v tx /e g with v rx = 0, reference figure 2. from equation 7 with v rx = 0 substituting equation 13 into equation 12 and simplifying. by design, v tx = -v tr , therefore, a more useful form of the equation is rewritten in terms of v tx /v 2w . a voltage divider equation is written to convert from e g to v 2w as shown in equation 16. rearranging equation 16 in terms of e g , and substituting into equation 15 results in an equation for 2-wire to 4-wire gain that?s a function of the synthesized input impedance of the slic and the protection resistors (z tr ). to match a 600 ? line, z tr is set to 595 ? (eq 1, 107k/200+60) where r p is equal to 30.0 ? . this results in a 2-wire to 4-wire gain of 0.9 or -0.915db (eq 17, 595-60/595). notice that the phase of the 2-wire to 4-wire signal is in phase with the input signal and that the gain will always be less than one because of the protection resistors. transmit gain across the system the transmit gain across the system is defined as the gain from the phone or 2-wire side (v 2w ) to the pcm highway. setting the gain of the idt821054/64 will have to account for the attenuated signal through the unislic14. the system gain is entirely controlled by programming the idt821054/64. the idt821054/64 can program the transmit gain across the system in two ways (reference figure 3). ? the first is by programming the signal gain in its analog form. the analog transmit gain, also known as analog to digital (a/d) gain, can be programmed in the idt821054/64 to be either 0db or +6db. ? the second is by programming the signal gain (via. coefficients) when its in digital form. the digital form of the transmit path can be programmed from -3db to +12db with minimum 0.1db steps. this results in a possible transmit gain (a/d) programming range from -3db to +18db. note: analog gain brings less noise than digital gain. when allocating the codec gain, the majority of the required gain should be preformed in the analog stage. reference section titled ?information required for idt to calculate idt821054/64 codec dsp coefficients? for information on obtaining coefficients for your design. transhybrid balance g(4-4) transhybrid balance is a measure of how well the input signal is canceled (that being received by the slic) from the transmit signal (that being transmitted from the slic to the codec). without this function, voice communication would be difficult because of the echo. the transhybrid balancing filter inside the idt821054/64 is used to adjust transhybrid balance to ensure the echo cancellation meets the itu-t specifications. the coefficient for echo cancellation is ecf. frequency response correction the frr filter in the receive path and the frx filter in the transmit path can be programmed to correct any frequency distortion caused by the impedance matching filters. the coefficients of frequency response correction are frr for receive path and frx for the transmit path. e ? g z l i m 2r p i m v tr ? + + 0 = loop equation (eq. 12) v tr i m z tr 2r p ? () ? = (eq. 13) e g i m z l z tr + () = (eq. 14) g 2-4 = v tx e g ---------- = i m z tr 2r p ? () i m z l z tr + () --------------------------------------- - z tr 2r p ? () z l z tr + () --------------------------------- = (eq. 15) v 2w = z tr z tr z l + ------------------------ ?? ?? ?? e g (eq. 16) g 2-4 = v tx v 2w ----------- - = z tr - 2r p z tr ----------------------------- 600 60 ? 600 ---------------------- 0.9 == (eq. 17) an9999
4 information required for idt to calculate idt821054/64 codec dsp coefficients for idt to calculate idt821054/64 dsp coefficient, customers should provide the following information about their subscriber line card: ? accurate slic pspice model. it can be provided in .lib file or pspice schematic file. ? system impedance ? gain (transmit path and receive path) using the dsp coefficients provided by idt, the overall performance of the system will pass itu-t requirements. when the cof ram button is selected from the mpi operation general interface screen, the cof ram operation screen will appear (figure 4). from this screen, the user can configure all the coefficients for the current channel. reference design of the unislic14 and the idt821054/64 with a 600 ? load the design criteria is as follows: ? 4-wire to 2-wire gain (dr1/dd to v 2w ) equal 0db ? 2-wire to 4-wire gain (v 2w to dx1/du) equal 0db ? rp = 30 ? figure 5 gives the reference design using the intersil unislic14 and the idt821054/64 programmable quad pcm codec. also shown in figure 5 are the voltage levels at specific points in the circuit. impedance matching the 2-wire impedance is matched to the line impedance z 0 using equation 1, repeated here in equation 18. for a line impedance of 600 ? , z t equals: the closest standard value for z t is 107k ? . however, it would be very convenient and cost effective if system manufacturers can use only one type of line card to meet different impedance requirements and different gain requirements. the programmability of idt821054/64 can help system manufactures to reach this goal. by using different coefficients this reference design can meet both 600 ? and 200 ? + 680?||0.1 f impedance requirements. with the value of z t selected to be 107k ? 1% , the coefficients for transmit gain (a/d) and receive gain of zero (with a line impedance of 600 ? ) is given in table 1. figure 3. receive gain g(4-2), transmit gain (2-4) dr1/dd dx1/du idt821054/64 vout1 pcm/gci interface dsp core channel 1 channel 2 channel 4 vin1 . . . analog gain 0db to -6db digital gain +6db to -12db analog gain 0db to +6db digital gain -6db to +12db receive path transmit path frr filter frx filter tip ring v rx v tx z l v 2w vs z o z tr v tr + - + - z t z t ptg floating r p 30 ? r p 30 ? intersil unislic14 c tx 0.47 f c rx 0.47 f (1 of 4) figure 4. coefficient ram operation screen z t 200 z tr 2r p ? () ? = (eq. 18) z t 200 600 60 ? () ? 108k ? == (eq. 19) an9999
5 specific implementation for china the design criteria for a china specific solution are as follows: ? desired line circuit impedance is 200 + 680//0.1 f ? receive gain (v 2w /(dr1/dd)) is -3.5db ? transmit gain ((dx1/du)/v 2w ) is 0db ? 0dbm0 is defined as 1mw into the complex impedance at 1020hz ?r p = 30 ? figure 6 gives the reference design using the intersil unislic14 and the idt821054/64 programmable quad codec. also shown in figure 6 are the voltage levels at specific points in the circuit. these voltages will be used to adjust the gains of the network. adjustment to get -3.5dbm0 at the load referenced to 600 ? the voltage equivalent to 0dbm0 into 811 ? (0dbm0 (811 ?) ) is calculated using equation 20 (811 ? is the impedance of complex china load at 1020hz). the gain referenced back to 0dbm0 (600 ?) is equal to: the adjustment to get -3.5dbm0 at the load referenced to 600 ? is: the voltage at the load (referenced to 600 ? ) is given in equation23: impedance matching contact idt for specific coefficiens for this design. figure 5. reference design of the unislic14 and the idt821054/64 with a 600 ? load impedance pcm bus 0dbm0 (600 ? ) 0.7745v rms 0dbm0 (600 ? ) 0.7745v rms 0dbm0 (600 ? ) 0.7745v rms 0dbm0 (600 ? ) 0.7745v rms 0dbm0 (600 ? ) 0.7745v rms g4-2 g2-4 -0.915dbm0 (600 ? ) 0.69714v rms z o = z l - 2 rp dr1/dd dx1/du idt821054/64 vout1 pcm/gci interface dsp core channel 1 channel 2 channel 4 vin1 . . . analog gain 0db digital gain 0db analog gain 0db digital gain +0.9db receive path transmit path reference table 1 for coefficients system requirements: impedance: 600 ? transmit gain (a/d): 0db receive gain (d/a): 0db tip ring v rx v tx z l v 2w vs z o z tr v tr + - + - z t z t ptg floating r p 30 ? r p 30 ? intersil unislic14 c tx 0.47 f c rx 0.47 f (1 of 4) 0dbm 811 ? () 10 v 2 811 0.001 () ----------------------------- - log 0.90055v rms == (eq. 20) gain 20 0.90055v rms 0.7745v rms -------------------------------------- log 1.309db == (eq. 21) adjustment 3.5dbm0 ? 1.309dbm0 + 2.19 ? db == (eq. 22) 2.19 ? dbm 600 ? () 10 v 2 600 0.001 () ----------------------------- - log 0.60196v rms == (eq. 23) an9999
6 i figure 6. reference design of the unislic14 and the idt821054/64 with china complex load impedance -2.19dbm0 (600 ? ) -2.19dbm0 (600 ? ) 0.60196v rms -2.19dbm0 (600 ? ) 0.60196v rms g4-2 g2-4 v pwro+ v pcmout 0.60196v rms 0dbm0 (600 ? ) 0.7745v rms 0.51769v rms -3.5dbm0 (600 ? ) -3.1dbm0 (600 ? ) 0.54176 rms dr1/dd dx1/du idt821054/64 vout1 pcm/gci interface dsp core channel 1 channel 2 channel 4 vin1 . . . analog gain 0db digital gain -2.19db analog gain 0db digital gain -0.4db receive path transmit path system requirements: impedance: 200 ? +600 ? ||0.1 f transmit gain (a/d): 0db receive gain (d/a): -3.5db contact idt for coefficients tip ring v rx v tx z l v 2w vs z o z tr v tr + - + - z t z t ptg floating r p 30 ? r p 30 ? intersil unislic14 c tx 0.47 f c rx 0.47 f (1 of 4) table 1. 600 ? coefficients, system gains: (transmit gain (0db), receive gain (0db)), codec analog gains: (transmit path +6db, receive path 0db) coefficient ram channel 1 imf: 04 00 ee ff 00 00 00 00 00 00 00 00 00 00 00 00 ecf: c2 08 00 00 00 00 00 0 00 00 a2 5e 75 d9 00 00 km: 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 act: d7 00 f9 ef 16 25 16 25 f9 ef d7 00 99 31 gtx ff 1f acr: ff 00 84 fe 49 3f 49 3f 84 fe ff 00 ce 84 grx 0c 03 coefficient ram channel 2 imf: 04 00 ee ff 00 00 00 00 00 00 00 00 00 00 00 00 ecf: c2 08 00 00 00 00 00 0 00 00 a2 5e 75 d9 00 00 km: 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 act: d7 00 f9 ef 16 25 16 25 f9 ef d7 00 99 31 gtx ff 1f acr: ff 00 84 fe 49 3f 49 3f 84 fe ff 00 ce 84 grx 0c 03 coefficient ram channel 3 imf: 04 00 ee ff 00 00 00 00 00 00 00 00 00 00 00 00 ecf: c2 08 00 00 00 00 00 0 00 00 a2 5e 75 d9 00 00 km: 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 act: d7 00 f9 ef 16 25 16 25 f9 ef d7 00 99 31 gtx ff 1f acr: ff 00 84 fe 49 3f 49 3f 84 fe ff 00 ce 84 grx 0c 03 an9999
7 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com coefficient ram channel 4 imf: 04 00 ee ff 00 00 00 00 00 00 00 00 00 00 00 00 ecf: c2 08 00 00 00 00 00 0 00 00 a2 5e 75 d9 00 00 km: 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 act: d7 00 f9 ef 16 25 16 25 f9 ef d7 00 99 31 gtx ff 1f acr: ff 00 84 fe 49 3f 49 3f 84 fe ff 00 ce 84 grx 0c 03 table 1. 600 ? coefficients, system gains: (transmit gain (0db), receive gain (0db)), codec analog gains: (transmit path +6db, receive path 0db) (continued) an9999
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